1. Field of the Invention
The present invention relates to the manufacturing of semiconductive chips including at least one area corresponding to power components and at least one area corresponding to logic components.
2. Discussion of the Related Art
For a long time, designers and manufacturers of semiconductor components have attempted to integrate, on the same chip logic circuits and at least one vertical power component having a first electrode located on the upper surface and a second electrode located on the lower surface of the chip. The problem of the isolation of the logic circuits powered by low voltages and conducting small currents, which are likely to be disturbed by the high voltages and currents in the power components, then arises. Conventional solutions, which consist of using junction isolations, are never totally efficient. It has thus been devised to form the logic circuits in a portion dielectrically insulated from the substrate in which the power components are made. An example of such a solution has been described in 1985 by Joseph Borel in European patent 0220974. However, although they are theoretically attractive, the various suggested structures have had difficulties to be implemented, whereby, in practice, no power components associated with logic circuits with a complete or partial dielectric insulation from the power portion are presently available for sale.